1. Field of the Invention
The present invention relates to a plurality of column electrode driving circuits used in a display device such as, for example, a liquid crystal display device, and a display device including the plurality of column electrode driving circuits.
2. Description of the Related Art
A liquid crystal display device includes a pair of glass substrates and a liquid crystal layer interposed between the pair of glass substrates. FIG. 5 is a plan view illustrating a schematic structure of one of the glass substrates of a conventional liquid crystal display device. The one of the glass substrates will be referred to as a “control glass substrate”. The control glass substrate is indicated with reference numeral 21. The control glass substrate 21 includes a display section 21a. The liquid crystal layer is interposed in a plane corresponding to the display section 21a. The control glass substrate 21 has a plurality of row electrodes (gate electrodes) 205 and a plurality of column electrodes (source electrodes) 206 thereon. The plurality of row electrodes 205 are parallel to each other, and the plurality of column electrodes 206 are parallel to each other. The plurality of row electrodes 205 and the plurality of column electrodes 206 are perpendicular to each other. The other glass substrate (not shown; hereinafter, referred to as a counter glass substrate) has a common electrode provided on substantially the entirety of a surface thereof, the surface being closer to the liquid crystal layer than the other surface of the counter glass substrate.
The control glass substrate 21 has a lengthy gate substrate 29 thereon along one side thereof. The control glass substrate 21 has a lengthy source substrate 25 along a side thereof, which is perpendicular to the side along which the gate substrate 29 is provided. There is a gap between the display section 21a and the gate substrate 29. There is a gap between the display section 21a and the source substrate 25. A plurality of row electrode driving circuits (gate driver ICs) 22, each for driving a plurality of row electrodes 205, are provided to straddle the gap between the gate substrate 29 and the display section 21a. A plurality of column electrode driving circuits (source driver ICs) 23, each for driving a plurality of column electrodes 206, are provided to straddle the gap between the source substrate 25 and the display section 21a. 
A control substrate 31 is provided in the vicinity of the gate substrate 29 and the source substrate 25. A timing controller IC 34 is mounted on the control substrate 31.
FIG. 6 is a block diagram illustrating an internal structure of the timing controller IC 34. The timing controller IC 34 includes an input buffer 34a for receiving a control data signal (for example, a display data signal regarding each of RGB colors in a color image displayed by the display section 21a, a clock signal CK, a horizontal synchronous signal HS, a vertical synchronous signal VS, an enable signal ENAB, or the like).
The timing controller IC 34 further includes a timing control section 34b for outputting a column electrode driving timing signal and a row electrode driving timing signal based on the control data signal which is input to the input buffer 34a, a source-side output buffer 34c for outputting a display data signal in synchronization with the column electrode driving timing signal which is output from the timing control section 34b, and a gate-side output buffer 34d for outputting the row electrode driving timing signal which is output from the timing control section 34b. 
The timing control section 34b generates a column electrode driving timing signal such as, for example, a source start pulse (SSP) or a source clock (SCK) for each column electrode driving circuit 23 based on the control data signal which is output from the input buffer 34a. The timing control section 34b outputs each column electrode driving timing signal generated by the timing control section 34b to the source-side output buffer 34c. Then, the source-side output buffer 34a outputs the received column electrode driving timing signal to a respective column electrode driving circuit 23 on the source substrate 25 via a line 25a provided on a flexible printed circuit board (FPC) 33 (FIG. 5) and on the source substrate 25.
Similarly, the timing control section 34b also generates a row electrode driving timing signal (or a scanning signal) such as, for example, a gate start pulse (GSP) or a gate clock (GCK) for each row electrode driving circuit 22 based on the control data signal which is output from the input buffer 34a. The timing control section 34b outputs each row electrode driving timing signal generated by the timing control section 34b to the gate-side output buffer 34d. Then, the gate-side output buffer 34d outputs the received row electrode driving timing signal to a respective row electrode driving circuit 22 on the gate substrate 29 via a line 29a provided on an FPC 32 (FIG. 5) and on the gate substrate 29.
As described above, the timing controller IC 34 generates a column electrode driving timing signal for driving each column electrode driving circuit 23 and a row electrode driving timing signal for driving each row electrode driving circuit 22, and outputs a display data signal to each column electrode driving circuit 23 based on the control data signal and the column electrode driving timing signal in synchronization with the column electrode driving timing signal.
In the liquid crystal display device having the above-described structure, each row electrode driving circuit 22 and each column electrode driving circuit 23 are driven based on the respective row electrode driving timing signal and the respective column electrode driving timing signal which are generated by the timing controller IC 34 provided on the control substrate 31. Therefore, the timing controller IC 34 needs to have a sufficiently large size and the control substrate 31 also needs to have a large size for mounting the timing controller IC 34 thereon.
Recently, display devices including liquid crystal display devices have increased in size and become of higher definition. This has required the bus lines on the control substrate 31 and the source substrate 25 to be longer, which increases a load capacitance of each bus line and also increases the number of the column electrode driving circuits 23 connected to each bus line. As a result, the fan-out required of the output buffers 34c and 34d in the timing controller IC 34 needs to be increased, and stricter timing setting is also required.
In order to output the column electrode driving timing signals and the row electrode driving timing signals from the timing controller IC 34 to the respective column electrode driving circuit 22 and the respective row electrode driving circuit 23, the FPC 32 for connecting the control substrate 31 and the gate substrate 29 and the FPC 33 for connecting the control substrate 31 and the source substrate 25 are required. The line 29a provided on the gate substrate 29 and the line 25a provided on the source substrate 25 are also required. These requirements have significant influences on the external appearance of the display devices including an increase in the thickness.
Since the control substrate 31 and the gate substrate 29 are connected to each other using the FPC 32 and the control substrate 31 and the source substrate 25 are connected to each other using the FPC 33, the structure of the display device is complicated and the assembly process becomes more difficult. As a result, the production cost of the display device is raised.
Japanese Laid-Open Publication No. 11-194713 discloses a display device having the following structure. A column electrode driving circuit (source driver) is provided with a timing generation circuit, and the column electrode driving circuit and a row electrode driving circuit (gate driver) are operated based on the column electrode driving timing signal and the row electrode driving timing signal which are generated by the timing generation circuit. Such a structure is simpler and prevents enlargement of the entire size of the device.
Accordingly, in the above-described display device including a plurality of column electrode driving circuits (source drivers) and a plurality of row electrode driving circuits (gate drivers), it can be considered that one of the plurality of column electrode driving circuits is provided with a timing generation circuit, so that a column electrode driving timing signal and a row electrode driving timing signal generated by the timing generation circuit is supplied to each of the plurality of column electrode driving circuits and each of the plurality of row electrode driving circuits.
FIG. 7 is a plan view of a control glass substrate 210. The control substrate 210 includes a plurality of column electrode driving circuits (source drivers). One column electrode driving circuit 23A, among the plurality of column electrode driving circuits 23, includes a timing controller IC 34. Such a structure is not practical for the following reason. The column electrode driving circuit 23A including the timing controller IC 34 needs to have a large output buffer in order to output a column electrode driving timing signal and a row electrode driving timing signal to the other column electrode driving circuits 23 and the other row electrode driving circuits 22, respectively.
In the display device disclosed in Japanese Laid-Open Publication No. 11-194713, the column electrode driving circuits and the row electrode driving circuits are mounted by COG (chip on glass). In such a case, the column electrode driving circuits and the row electrode driving circuits cannot be easily positionally aligned with lines provided on the glass substrate. Therefore, such a display device is not easily produced. In the Japanese Laid-Open Publication No. 11-194713, lines are provided in the display section in order to avoid interference between the lines. This structure undesirably requires an area of the glass substrate around the display section to be enlarged.